1. Field of the Invention
The invention relates to a gate driver and shift register, and more particularly, to a gate driver and shift register that can suppress glitches caused by the coupling effect of parasitic capacitors of a transistor.
2. Description of the Prior Art
Generally, a display panel includes a plurality of pixels, at least one gate driver, and at least one source driver. The gate driver includes a plurality of stages of shift registers and is used to provide a plurality of gate driving signals for turning on and off the pixels. The source driver is used to write the data into the turned-on pixels.
FIG. 1 shows the shift register 100 according to prior art and FIG. 2 shows the timing diagram of the shift register 100 in FIG. 1. The shift register 100 is a bidirectional shift register, which includes switches T1A to T1G. The first terminal of the switch T1A receives the first selective control signal U2D, the second terminal of the switch T1A is coupled to the node QN, and the control terminal of the switch T1A receives the gate driving signal GN−1. The first terminal of the switch T1B receives the second selective control signal D2U, the second terminal of the switch T1B is coupled to the node QN, and the control terminal of the switch T1B receives the gate driving signal GN+1. The gate driving signal GN−1 is the output signal of the shift register that is one stage prior to the shift register 100, and the gate driving signal GN+1 is the output signal of the shift register that is one stage next to the shift register 100.
The first terminal of the switch T1C receives the clock signal CK. The second terminal of the switch T1C is coupled to the output terminal Out of the shift register 100 to output the gate driving signal GN. The first terminal of the capacitor C1 is coupled to the node QN, and the second terminal of the capacitor C1 is coupled the output terminal OUT. The first terminal of the capacitor C2 receives the clock signal CK, the second terminal of the capacitor C2 is coupled to the node PN. The first terminal of the switch T1D is coupled to the node PN, the second terminal of the switch T1D is coupled to the system voltage terminal VSS, and the control terminal of the switch T1D is coupled to the node QN. The system voltage terminal VSS is used to provide the low gate voltage VGL. The switch T1D controls the electrical connection between the node PN and the low gate voltage VGL according to the voltage level of the node QN. The first terminals of the switches T1E and T1F are coupled to the node QN and the output terminal Out of the shift register 100 respectively, and the second terminals of the switches T1E and T1F are both coupled to the system voltage terminal VSS. In addition, the control terminals of the switches T1E and T1F are coupled to the node PN so the switches T1E and T1F are turned on or turned off by control of the voltage level of the node PN. Furthermore, the first terminal of the switch T1G is coupled to the output terminal Out of the shift register 100, the second terminal of the switch T1G is coupled to the system voltage terminal VSS, and the control end of the switch T1G receives another clock signal XCK. The voltage levels of the clock signal XCK and the clock signal CK switch between the high gate voltage VGH and low gate voltage VGL.
With the first selective control signal U2D at the high gate voltage VGH and the second selective control signal D2U at the low gate voltage VGL, during the period of T1 in FIG. 2, the gate driving signal GN−1 is pulled up to the high gate voltage VGH, the switch T1A is turned on and the switch T1B is turned off so the voltage level of the node QN is also pulled up to the high gate voltage VGH. Meanwhile, the switches T1C, T1D and T1G are also turned on because the voltage level of the node QN and the clock signal XCK are at the high gate voltage VGH. However, since the clock signal CK is at low gate voltage VGL, the voltage levels of the gate driving signal GN and the node PN are kept at low gate voltage VGL. The switches T1E and T1F are turned off since the voltage level of the node PN is at low gate voltage.
During the period of T2 in FIG. 2, the gate driving signal GN−1 is pulled down to the low gate voltage VGL, the clock signal CK is at the high gate voltage VGH, and the clock signal XCK is at the low gate voltage VGL. The switches T1A and T1B are turned off and the switch T1C is still turned on so the gate driving signal GN is pulled up to the high gate voltage VGH. The voltage level of the node QN is raised to about two times of the high gate voltage VGH due to the coupling effect of the capacitor C1. The switch T1D is turned on so the voltage level of the node PN is kept at the low gate voltage VGL. Meanwhile, the switches T1E and T1F are turned off.
During the period of T3 in FIG. 2, the gate driving signal GN−1 is still at the low gate voltage VGL, the gate driving signal GN+1 is at the high gate voltage VGH, the clock signal CK is at the low gate voltage VGL, and the clock signal XCK is at the high gate voltage VGH. The switch T1A is turned off, and the switches T1B and are T1G are turned on. Since the switch T1B is turned on, the voltage level of the node QN is pulled down to the same voltage level of the second selective control signal D2U (namely, the low gate voltage VGL). Also, the gate driving signal GN of the shift register 100 is pulled down to the low gate voltage VGL because the switch T1G is turned on. Since the voltage level of the node QN is pulled down, the switches T1C and T1D are turned off. In addition, due to the clock signal CK, the voltage level of the node PN is pulled down to the low gate voltage VGL, which further turns off the switches T1E and T1F.
During the period of T4 in FIG. 2, the gate driving signals GN−1 and GN+1 are at the low gate voltage VGL, the clock signal CK is at the high gate voltage VGH, and the clock signal XCK is at the low gate voltage VGL. The switches T1A, T1B, T1C, T1D, and T1G are all turned off. However, due to the coupling effect caused by the parasitic capacitor of the switch T1C, a glitch P can be easily generated on the node QN. Although the voltage level of the node QN can be pulled down by the switches T1E and T1F, the switches T1E and T1F may need a response time to be fully turned on and may not be able to suppress the glitch P effectively since the glitch P is generated instantly when the voltage level of the clock signal CK changes to the high gate voltage VGH. Under this situation, the waveform of the gate driving signal GN of the shift register 100 can be triggered by mistake and may further cause wrong charging of the pixels driven by the gate driving signal GN.